In the integrated circuit (IC) chip fabrication industry, circuitry is formed in a semiconductor substrate using photolithography. One challenge that the industry faces is that large circuit designs are too large to place as a whole on the reticles used in photolithography. One remedy to this issue is leveraging the redundancy within the IC chip design to break the design up into a subset of smaller unique dissected regions. When resolved in multiple regions, the dissected regions can form the completed large IC chip layout on a wafer by a process commonly referred to as “stitching”. Stitching includes placing the dissected IC chip (stitched) regions onto a reticle and performing multiple exposures on the wafer in order to complete the final whole IC chip image.
With the increased use of stitched IC layouts and the improved control of mating stitched circuitry regions, it is becoming difficult to easily locate stitch region boundaries within an IC layout for process control metrology. Current approaches place marking shapes within the kerf of the wafers to mark boundaries.